DTM65525B
2 GB, 240-Pin DDR2 FB-DIMM
Document 06530, Revision A, 20-Apr-09, Dataram Corporation © 2009 Page 7
Differential Receiver Input Specification
Parameter Symbol
MIN MAX Units
Differential peak-to-peak input voltage
VRX-DIFFp-p =2 * | VRX-D+ - VRX-D- |
VRX-DIFFp-p_L(1)
170 1300 mV
Maximum single-ended voltage for EI condition, DC + AC
VRX-IDLE-SE(2,3,4)
--- 65 mV
Maximum single-ended voltage for EI condition, DC only
VRX-IDLE-SE-
DC(2,3,4,5)
--- 35 mV
Single-ended voltage (w.r.t. VSS) on D+/D-
VRX-SE(4)
-300 900 mV
Single-pulse peak differential input voltage
VRX-DIFF-PULSE(4,6)
85 --- mV
Amplitude ratio between adjacent symbols
1100mV < VRX-DIFFp-p ≤1300mV
VRX-DIFF-ADJ-
RATIO-HI(4,7)
--- 3
Amplitude ratio between adjacent symbols
VRX-DIFFp-p ≤1100mV
VRX-DIFF-ADJ-
RATIO(4,7)
--- 4
Maximum RX inherent timing error, 3.2 and 4 Gb/s
TRX-TJ-MAX(4,8,9)
--- 0.4 UI
Maximum RX inherent deterministic timing error, 3.2 and 4
Gb/s
TRX-DJ-DD(4,8,9,10)
--- 0.3 UI
Single-pulse width at zero-voltage crossing
TRX-PW-ZC(4,6)
0.55 --- UI
Single-pulse width at minimum-level crossing
TRX-PW-ML(4,6)
0.2 --- UI
Differential RX input rise/fall time, given by 20%-80% voltage
levels
TRX-RISE,TRX-FALL
50 --- ps
Common mode of the input voltage
Defined as: VRX-CM = DC(avg) of | VRX-D+ + VRX-D- |/2
VRX-CM(1,11)
120 400 mV
AC peak-to-peak common mode of input voltage VRX-CM-
AC = Max | VRX-D+ + VRX-D- |/2 - Min | VRX-D+ + VRX-D- |/2
VRX-CM-ACp-p(1)
--- 270 mV
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p
VRX-CM-EH-Ratio(12)
--- 45 %
Differential return loss
Measured over 0.1 GHz to 2.4GHz
RLRX-DIFF
9 --- dB
Common mode return loss
Measured over 0.1 GHz to 2.4GHz
RLRX-CM
6 --- dB
RX termination resistance
RRX(13)
41 55 Ω
D+/D- RX resistance difference
RRX-Match-DC = 2*| RRX-D+ - RRX-D- |/( RRX-D+ + RRX-D- )
RRX-Match-DC
--- 4 %
Lane-to-lane PCB skew at RX
Lane to Lane PCB skew at the Receiver that must be
tolerated.
LRX-PCB-SKEW(14)
--- 6 UI
Minimum RX Drift Tolerance
TRX-DRIFT(15) 400
--- ps
Minimum data tracking 3dB bandwidth
FTRK(16) 0.2
--- MHz
Electrical idle entry detect time
TEI-ENTRY -
DETECT(17)
---
60 ns
Electrical idle exit detect time
TEI-EXIT-DETECT ---
30 ns
Bit Error Ratio
BER(18)
--- 10
-12
(11 pages)
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